Data Sheet
HCPL-7723/0723
50-MBd 2-ns PWD High-Speed CMOS
Optocoupler
Description
Available in either 8-pin DIP or SO.8 package style
respectively, the Broadcom® HCPL-7723 or HCPL-0723
optocoupler utilize the latest CMOS IC technology to
achieve outstanding speed performance of minimum
50 MBd data rate and 2-ns maximum pulse width distortion.
Features
Basic building blocks of HCPL-7723/0723 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC, which
supplies current to the LED. The detector IC incorporates an
integrated photodiode, a high-speed transimpedance
amplifier, and a voltage comparator with an output driver.
CAUTION! It is advised that normal static precautions be
taken in handling and assembly of this
component to prevent damage and/or
degradation, which may be induced by ESD.
The components featured in this data sheet are
not to be used in military or aerospace
applications or environments.
Applications
Broadcom
+5V CMOS compatibility
High speed: 50 MBd min.
2-ns max. pulse width distortion
22-ns max. propagation delay
16 ns max. propagation delay skew
10 kV/µs min. common mode rejection
–40 to 85°C temperature range
Safety and regulatory approvals:
– UL recognized:
5000 Vrms for 1 min. per UL1577 for HCPL-7723
for option 020
3750 Vrms for 1 min. per UL1577 for HCPL-0723
– CSA component acceptance notice #5
– IEC/EN/DIN EN 60747-5-5
Viorm = 630 Vpeak for HCPL-7723 option 060
Viorm = 567 Vpeak for HCPL-0723 option 060
Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
Multiplexed data transmission
High-speed digital input/output
Computer peripheral interface
Microprocessor system interface
AV02-0643EN
September 26, 2017
HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Functional Diagram
Truth Table
**VDD1
1
8
VDD2**
VI
2
7
NC*
NC*
3
6
VO
5
GND2
VI Input
LED1
VO Output
H
L
OFF
ON
H
L
IO
LED1
4
GND1
SHIELD
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.01 to 0.1 μF BYPASS CAPACITOR MUST BE CONNECTED AS
CLOSE AS POSSIBLE BETWEEN PINS 1 AND 4, AND 5 AND 8.
Package Outline Drawings
HCPL-7723 8-Pin DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
8
AVAGO
LEAD-FREE
DATE CODE
PIN 1
1.19 (0.047) MAX.
•
1
7
7.62 ± 0.25
(0.300 ± 0.010)
6
5
DEVICE PART NUMBER
TEST RATING CODE
A NNNN Z
YYWW
EEE P
2
3
6.35 ± 0.25
(0.250 ± 0.010)
UL LOGO
4
SPECIAL PROGRAM CODE
LOT ID
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
Broadcom
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
HCPL-7723 Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
2
1
3
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
+ 0.076
- 0.051
+ 0.003)
(0.010
- 0.002)
0.254
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
HCPL-0723 Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
1.91
(0.075)
0.64
(0.025)
3.937 ± 0.127
(0.155 ± 0.005)
8
7
6
5
NNNN Z
YYWW
EEE
DEVICE PART
NUMBER
LEAD-FREE
•
PIN 1
1
2
3
TEST RATING CODE
DATE CODE
LOT ID
4
0.406 ± 0.076
(0.016 ± 0.003)
3.95
(0.156)
5.994 ± 0.203
(0.236 ± 0.008)
1.270 BSC
(0.050)
1.27
(0.5)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
1.524
(0.060)
* Total package length (inclusive of mold flash)
5.207 ± 0.254 (0.205 ± 0.010)
Dimensions in Millimeters (Inches).
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
Lead coplanarity = 0.10 mm (0.004 inches) max.
Option number 500 not marked.
Broadcom
7.49
(0.295)
0.432
45° X (0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
AV02-0643EN
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Device Selection Guide
8-Pin DIP (300 mil)
Small Outline SO-8
HCPL-7723
HCPL-0723
Ordering Information
HCPL-0723 and HCPL-7723 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
.
Option
RoHS
Part Number Compliant
HCPL-7723
HCPL-0723
Non RoHS
Compliant
Package
Surface
Mount
Gull
Wing
-000E
no option
-300E
-300
X
X
-500E
-500
X
X
-020E
-020
-320E
-320
X
X
-520E
-520
X
X
-060E
-060
-360E
-360
X
X
X
X
-560E
-560
-000E
no option
Tape and
Reel
UL5000
Vrms /
1 Minute
Rating
IEC/EN/DIN
EN 60747-5-5
300 mil DIP-8
SO-8
Quantity
50 per tube
50 per tube
X
X
X
1000 per reel
X
50 per tube
X
50 per tube
X
1000 per reel
X
50 per tube
X
50 per tube
X
X
-500E
-500
X
-060E
-060
X
-560E
-560
X
1000 per reel
100 per tube
X
X
1500 per reel
X
100 per tube
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column
to form an order entry.
Example 1:
HCPL-7723-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Example 2:
HCPL-0723 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.
NOTE:
Broadcom
The notation #XXX is used for existing products, while (new) products launched since July 15, 2001 and RoHS
compliant will use –XXXE.
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Regulatory Information
The HCPL-7723/0723 have been approved by the following organizations:
UL — Recognized under UL1577, component recognition program, File E55361.
CSA — Approval under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5 — Approved with Maximum Working Insulation Voltage:
– Viorm = 567 Vpeak for HCPL-0723
– Viorm = 630 Vpeak for HCPL-7723
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Insulation and Safety Related Specifications
Value
Parameter
Symbol
7723
0723
Unit
Minimum External Air Gap
(Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(I02)
7.4
4.8
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.08
0.08
mm
Insulation thickness between emitter and detector;
also known as distance through insulation.
≥175
≥175
V
IIIa
IIIa
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
Broadcom
CTI
Conditions
DIN IEC 112/VDE 0303 Part 1.
Material Group (DIN VDE 0110, 1/89, Table 1).
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
All Broadcom data sheets report the creepage and clearance inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements.
However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified
for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board
between the solder fillets of the input and output leads must be considered. There are recommended techniques such as
grooves and ribs, which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on factors such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060)
Characteristic
Description
Symbol
HCPL-7723
HCPL-0723
I – IV
I – III
I – IV
I – IV
I – III
I – III
55/85/21
55/85/21
2
2
VIORM
630
567
Vpeak
Input to Output Test Voltage, Method
VIORM x 1.875 = VPR, 100% Production Test with tm = 1s,
Partial Discharge < 5 pC
VPR
1181
1063
Vpeak
Input to Output Test Voltage, Method aa
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10s,
Partial Discharge < 5 pC
VPR
1008
907
Vpeak
VIOTM
8000
6000
Vpeak
TS
PS, OUTPUT
175
230
600
150
150
600
°C
mA
mW
RS
≥109
≥109
Ω
Installation Classification per DIN VDE 0110/39, Table 1
For Rated Mains Voltage ≤ 150Vrms
For Rated Mains Voltage ≤ 300Vrms
For Rated Mains Voltage ≤ 600Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
ba
Highest Allowable Overvoltage (Transient Overvoltage tini = 60s)
Safety-Limiting Values – Maximum Values Allowed in the Event of a Failure
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500V
IS, INPUT
Unit
a. Refer to the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/
EN/DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
NOTE:
Broadcom
These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the
safety data is ensured by means of protective circuits.
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
Storage Temperature
TS
–55
125
°C
Ambient Operating Temperaturea
TA
–40
85
°C
VDD1, VDD2
0
6.0
V
Input Voltage
VI
–0.5
VDD1 + 0.5
V
Output Voltage
VO
–0.5
VDD2 + 0.5
V
Average Output Current
IO
—
10
mA
Supply Voltages
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane.
Solder Reflow Temperature Profile
See Solder Reflow Profile section.
a. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Unit
TA
–40
85
°C
VDD1, VDD2
4.5
5.5
V
Logic High Input Voltage
VIH
2.0
VDD1
V
Logic Low Input Voltage
VIL
0.0
0.8
V
tir, tif
—
1.0
ms
Ambient Operating Temperature
Supply Voltages
Input Signal Rise and Fall Times
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5V.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Currenta
IDD1L
—
8.4
10
mA
VI = 0V; Figure 1
Logic High Input Supply Currenta
IDD1H
—
0.6
3
mA
VI = VDD1; Figure 2
Output Supply Current
IDD2L
—
2.1
5
mA
Figure 3
IDD2H
—
2.0
5
mA
Figure 4
II
–10
—
10
μA
VOH
4.4
5.0
—
V
IO = –20 μA, VI = VIH
4.0
4.8
—
V
IO = –4 mA, VI = VIH
—
0
0.1
V
IO = 20 μA, VI = VIL
—
0.5
1.0
V
IO = 4 mA, VI = VIL
Logic Low Input Supply
Input Current
Logic High Output Voltage
Logic Low Output Voltage
VOL
Test Conditions
a. The LED is ON when VI is low and OFF when VI is high.
Broadcom
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5V.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Propagation Delay Time to Logic Low
Outputa
tPHL
—
16
22
ns
CL = 15 pF CMOS Signal Levels; Figure 5
Propagation Delay Time to Logic High
Outputa
tPLH
—
16
22
ns
CL = 15 pF CMOS Signal Levels; Figure 5
Pulse Width
PW
20
—
—
ns
CL = 15 pF CMOS Signal Levels
50
—
—
MBd
CL = 15 pF CMOS Signal Levels
|PWD|
—
1
2
ns
CL = 15 pF CMOS Signal Levels; Figure 6
tPSK
—
—
16
ns
CL = 15 pF CMOS Signal Levels
Output Rise Time (10% to 90%)
tR
—
8
—
ns
CL = 15 pF CMOS Signal Levels
Output Fall Time (90% to 10%)
tF
—
6
—
ns
CL = 15 pF CMOS Signal Levels
Common Mode Transient Immunity at
Logic High Outputd
|CMH|
10
15
—
kV/μs
VCM = 1000V, TA = 25°C,
VI = VDD1, VO > 0.8 VDD2
Common Mode Transient Immunity at
Logic Low Outputd
|CML|
10
15
—
kV/μs
VCM = 1000V, TA = 25°C,
VI = 0V, VO < 0.8V
Maximum Data Rate
Pulse Width Distortionb |tPHL - tPLH|
Propagation Delay Skewc
a. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
b. PWD is defined as |tPHL – tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
c. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
d. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
Broadcom
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Package Characteristics
All typical specifications are at TA = 25°C.
Parameter
Input-Output Momentary
Withstand Voltagea, b, c
Symbol
Min.
Typ.
Max.
Unit
VISO
3750
—
—
Vrms
Option 020
5000
—
—
–0723
3750
—
—
–7723
Test Conditions
RH ≤ 50%, t = 1 min, TA = 25°C
Input-Output Resistancea
RI-O
—
1012
—
Ω
VI-O = 500 Vdc
Input-Output Capacitance
CI-O
—
0.6
—
pF
f = 1 MHz
CI
—
3.0
—
pF
θjci
—
145
—
°C/W
—
160
—
—
145
—
—
135
—
—
—
150
Input Capacitanced
Input IC Junction-to-Case
Thermal Resistance
–7723
Output IC Junction-to-Case
Thermal Resistance
–7723
–0723
θjco
–0723
Package Power Dissipation
PPD
Thermocouple located at center
underside of package
°C/W
mW
a. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
b. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage≥ 4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 μA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection
current limit. II-O ≤ 5 μA.)
c. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Broadcom Application Note 1074,
Optocoupler Input-Output Endurance Voltage.
d. CI is the capacitance measured at pin 2 (VI).
Broadcom
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Figure 1: Typical Logic Low Input Supply Current vs.
Temperature
Figure 2: Typical Logic High Input Supply Current vs.
Temperature
0.6
IDD1H - LOGIC HIGH INPUT SUPPLY
CURRENT (mA)
IDD1L - LOGIC LOW INPUT SUPPLY
CURRENT (mA)
9.0
8.5
8.0
7.5
7.0
6.5
-40
-20
0
20
40
TA (°C)
60
80
IDD2H - LOGIC HIGH OUTPUT SUPPLY
CURRENT (mA)
IDD2L - LOGIC LOW OUTPUT SUPPLY
CURRENT (mA)
2.0
1.5
1.0
-20
0
20
40
TA (°C)
60
80
100
Figure 5: Typical Propagation Delay vs. Temperature
0
20
40
TA (°C)
60
80
100
2
1.5
20
PWD (ns)
18
16
14
T plh
T phl
12
-20
0
20
40
TA (°C)
60
80
-40
-20
0
20
40
TA (°C)
60
80
100
Figure 6: Typical Pulse Width Distortion vs. Temperature
22
Tphl, Tplh (ns)
-20
2.5
1
-40
Broadcom
-40
3
2.5
-40
0.45
Figure 4: Typical Logic High Output Supply Current vs.
Temperature
3.0
10
0.5
0.4
100
Figure 3: Typical Logic Low Output Supply Current vs.
Temperature
0.55
100
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
TA (°C)
60
80
100
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HCPL-7723/0723 Data Sheet
50-MBd 2-ns PWD High-Speed CMOS Optocoupler
Application Information
Bypassing and PC Board Layout
The HCPL-7723/0723 optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL7723/0723 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs.
As shown in Figure 7, the only external components required for proper operation are two bypass capacitors. Capacitor
values should be between 0.01 μF and 0.1 μF. Each capacitor should be placed as close as possible to the input and output
power-supply pins of the optocoupler.
Figure 7: Functional Diagram
VDD1
1
C1
VI
C2
2
GND1
VDD2
8
7 NC
NC 3
6
4
5
VO
GND2
C1, C2 = 0.01 μF TO 0.1 μF
Broadcom
AV02-0643EN
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Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks
of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU.
Copyright © 2017 by Broadcom. All Rights Reserved.
The term “Broadcom” refers to Broadcom Limited and/or its subsidiaries. For more information, please visit
www.broadcom.com.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does
not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
